Optimizing for Best Power During Place and Route in Low Power SoC Designs

Tackling low power challenges in place-and-route for better overall PPA

Design teams will always strive to achieve the best possible performance, power and area (PPA). As process technologies introduce greater challenges to power and as more applications strive for better power management, having tools and new methodologies to better manage this metric has become ever more essential. Aprisa helps designers converge on the best PPA possible.

Realize best power using activity-based placement and routing for lower dynamic power

By starting with the power metric as the top goal during optimization, the place-and-route flow can achieve the best possible power for that node, library, design specs, and optimize from that point to reach the timing target.

When design engineers use Aprisa's PowerFirst, they aren't using a feature but a methodology to optimize the design to reduce internal, switching, and leakage power of the most power-sensitive designs while minimizing tradeoffs. Learn more in the ebook.